The proliferation of multi-core processors in desktop and in the mobile computing environments is leading to a wider adoption of shared-memory and message passing parallel programming. While the performance benefits of writing parallel code for these platforms is undeniable, ensuring correct behavior is very hard. Consequently, the natural direction for future multicore processors is to add hardware features to support and facilitate the development of low-overhead correctness tools and techniques for parallel programs. HPPC will bring together researchers and practitioners doing innovative work in the area of hardware features to assist parallel program correctness during development or production.
This workshop will be held jointly with the Micro-44 conference, which will take place in Porto Alegre, Brazil, December 3-7, 2011
| Submissions: | September 16, 2011 |
| Notification: | October 28, 2011 |
| Event: | December 4, 2011-December 4, 2011 |