The On-chip communication system represents one of the most important elements which determine the overall performance, cost, reliability, and energy consumption of a modern multi-processor system-on-chip (MPSoC). The role played by the communication infrastructure is predicted to become even more and more important in the future multi-core computing nodes. Several issues like communication errors (due to crosstalk, electromagnetic interference, inter-symbol interference, etc.), link latency, link power dissipation, etc., that were considered negligible in the previous technologies, are dominant in current and next generation MPSoC. In addition, as we approach the many-cores era, in which hundreds or thousands of communicating on-chip cores represent the basic scenario, scalability issues must be properly addressed to meet performance, power and reliability requirements which characterize future ambient intelligent applications. The network-on-chip (NoC) paradigm is considered as the most viable solution for designing on-chip communication systems wich will be able to handle all the above issues satisfactorily. The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.
| Submissions: | September 18, 2011 |
| Notification: | October 18, 2011 |
| Event: | December 3, 2011-December 3, 2011 |