Design and Characterization of the TERO-PUF on SRAM FPGAs

Cédric Marchand 0002, Lilian Bossuet, Abdelkarim Cherkaoui. Design and Characterization of the TERO-PUF on SRAM FPGAs. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016. pages 134-139, IEEE, 2016. [doi]

@inproceedings{0002BC16-0,
  title = {Design and Characterization of the TERO-PUF on SRAM FPGAs},
  author = {Cédric Marchand 0002 and Lilian Bossuet and Abdelkarim Cherkaoui},
  year = {2016},
  doi = {10.1109/ISVLSI.2016.18},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2016.18},
  researchr = {https://researchr.org/publication/0002BC16-0},
  cites = {0},
  citedby = {0},
  pages = {134-139},
  booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016},
  publisher = {IEEE},
  isbn = {978-1-4673-9039-2},
}