A Formally Verified System for Logic Synthesis - researchr publication authors

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Mark Aagaard, Miriam Leeser. A Formally Verified System for Logic Synthesis. In Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD 91, Cambridge, MA, USA, October 14-16, 1991. pages 346-350, IEEE Computer Society, 1991.

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