Clock Buffers, Nets, and Trees for On-Chip Communication: A Novel Network Access Technique in FPGAs

Adewale Adetomi, Godwin Enemali, Tughrul Arslan. Clock Buffers, Nets, and Trees for On-Chip Communication: A Novel Network Access Technique in FPGAs. In 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2017, Orlando / Buena Vista, FL, USA, May 29 - June 2, 2017. pages 219-222, IEEE Computer Society, 2017. [doi]

@inproceedings{AdetomiEA17-0,
  title = {Clock Buffers, Nets, and Trees for On-Chip Communication: A Novel Network Access Technique in FPGAs},
  author = {Adewale Adetomi and Godwin Enemali and Tughrul Arslan},
  year = {2017},
  doi = {10.1109/IPDPSW.2017.156},
  url = {https://doi.org/10.1109/IPDPSW.2017.156},
  researchr = {https://researchr.org/publication/AdetomiEA17-0},
  cites = {0},
  citedby = {0},
  pages = {219-222},
  booktitle = {2017 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2017, Orlando / Buena Vista, FL, USA, May 29 - June 2, 2017},
  publisher = {IEEE Computer Society},
  isbn = {978-1-5386-3408-0},
}