VHDL implementation of fast NxN multiplier based on vedic mathematic

Shamim Akhter. VHDL implementation of fast NxN multiplier based on vedic mathematic. In 18th European Conference on Circuit Theory and Design, ECCTD 2007, Seville, Spain, August 26-30, 2007. pages 472-475, IEEE, 2007. [doi]

@inproceedings{Akhter07-0,
  title = {VHDL implementation of fast NxN multiplier based on vedic mathematic},
  author = {Shamim Akhter},
  year = {2007},
  doi = {10.1109/ECCTD.2007.4529635},
  url = {https://doi.org/10.1109/ECCTD.2007.4529635},
  researchr = {https://researchr.org/publication/Akhter07-0},
  cites = {0},
  citedby = {0},
  pages = {472-475},
  booktitle = {18th European Conference on Circuit Theory and Design, ECCTD 2007, Seville, Spain, August 26-30, 2007},
  publisher = {IEEE},
  isbn = {978-1-4244-1341-6},
}