Tim Anderson, Sanjive Agarwala. Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors. In ICCD. pages 403-407, 2000. [doi]
@inproceedings{AndersonA00,
title = {Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors},
author = {Tim Anderson and Sanjive Agarwala},
year = {2000},
url = {http://computer.org/proceedings/iccd/0801/08010403abs.htm},
tags = {rule-based, caching},
researchr = {https://researchr.org/publication/AndersonA00},
cites = {0},
citedby = {0},
pages = {403-407},
booktitle = {ICCD},
}