A DSP ASIC design flow based on VHDL and ASIC-emulation

Jan Andersson. A DSP ASIC design flow based on VHDL and ASIC-emulation. In Proceedings EURO-DAC 95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995. pages 562-567, IEEE Computer Society, 1995. [doi]

Authors

Jan Andersson

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