A probabilistically analysable cache implementation on FPGA

Hassan Anwar, Chao Chen, Giovanni Beltrame. A probabilistically analysable cache implementation on FPGA. In IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015. pages 1-4, IEEE, 2015. [doi]

Authors

Hassan Anwar

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Chao Chen

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Giovanni Beltrame

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