Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors

Masayuki Arai, Kazuhiko Iwasaki. Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors. In Leon Alkalai, Timothy Tsai, Tomohiro Yoneda, editors, 17th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2011, Pasadena, CA, USA, December 12-14, 2011. pages 264-271, IEEE Computer Society, 2011. [doi]

@inproceedings{AraiI11,
  title = {Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors},
  author = {Masayuki Arai and Kazuhiko Iwasaki},
  year = {2011},
  doi = {10.1109/PRDC.2011.38},
  url = {http://doi.ieeecomputersociety.org/10.1109/PRDC.2011.38},
  researchr = {https://researchr.org/publication/AraiI11},
  cites = {0},
  citedby = {0},
  pages = {264-271},
  booktitle = {17th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2011, Pasadena, CA, USA, December 12-14, 2011},
  editor = {Leon Alkalai and Timothy Tsai and Tomohiro Yoneda},
  publisher = {IEEE Computer Society},
  isbn = {978-1-4577-2005-5},
}