Armaiti Ardeshiricham, Yoshiki Takashima, Sicun Gao, Ryan Kastner. VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive Information Flow Properties. In Lorenzo Cavallaro, Johannes Kinder, Xiaofeng Wang 0001, Jonathan Katz, editors, Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, CCS 2019, London, UK, November 11-15, 2019. pages 1623-1638, ACM, 2019. [doi]
@inproceedings{ArdeshirichamTG19,
title = {VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive Information Flow Properties},
author = {Armaiti Ardeshiricham and Yoshiki Takashima and Sicun Gao and Ryan Kastner},
year = {2019},
doi = {10.1145/3319535.3354246},
url = {https://doi.org/10.1145/3319535.3354246},
researchr = {https://researchr.org/publication/ArdeshirichamTG19},
cites = {0},
citedby = {0},
pages = {1623-1638},
booktitle = {Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, CCS 2019, London, UK, November 11-15, 2019},
editor = {Lorenzo Cavallaro and Johannes Kinder and Xiaofeng Wang 0001 and Jonathan Katz},
publisher = {ACM},
isbn = {978-1-4503-6747-9},
}