An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style - researchr publication references

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Abhijit Asati, Chandrashekhar. An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style. In IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, ICIIS 2008, Kharagpur, India, December 8-10, 2008. pages 1-6, IEEE, 2008. [doi]

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