Mikhail Asiatici, Paolo Ienne. Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. In 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, Valencia, Spain, June 14-18, 2021. pages 609-622, IEEE, 2021. [doi]
@inproceedings{AsiaticiI21,
title = {Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses},
author = {Mikhail Asiatici and Paolo Ienne},
year = {2021},
doi = {10.1109/ISCA52012.2021.00054},
url = {https://doi.org/10.1109/ISCA52012.2021.00054},
researchr = {https://researchr.org/publication/AsiaticiI21},
cites = {0},
citedby = {0},
pages = {609-622},
booktitle = {48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, Valencia, Spain, June 14-18, 2021},
publisher = {IEEE},
isbn = {978-1-6654-3333-4},
}