A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS

Samira Ataei, Matthew Gaalswyk, James E. Stine. A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS. In IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017. pages 1236-1239, IEEE, 2017. [doi]

@inproceedings{AtaeiGS17,
  title = {A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS},
  author = {Samira Ataei and Matthew Gaalswyk and James E. Stine},
  year = {2017},
  doi = {10.1109/MWSCAS.2017.8053153},
  url = {https://doi.org/10.1109/MWSCAS.2017.8053153},
  researchr = {https://researchr.org/publication/AtaeiGS17},
  cites = {0},
  citedby = {0},
  pages = {1236-1239},
  booktitle = {IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017},
  publisher = {IEEE},
  isbn = {978-1-5090-6389-5},
}