Timing Aware Interconnect Prediction Models for FPGAs

Shankar Balachandran, Dinesh Bhatia. Timing Aware Interconnect Prediction Models for FPGAs. In Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong, editors, Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005. pages 167-172, IEEE, 2005.

Authors

Shankar Balachandran

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Dinesh Bhatia

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