Felice Balarin, Gary York. Verilog HDL Modeling Styles for Formal Verification. In David Agnew, Luc J. M. Claesen, Raul Camposano, editors, Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL 93, sponsored by IFIP WG10.2 and in cooperation with IEE. Volume A-32 of IFIP Transactions, pages 453-465, North-Holland, 1993.
@inproceedings{BalarinY93,
title = {Verilog HDL Modeling Styles for Formal Verification},
author = {Felice Balarin and Gary York},
year = {1993},
tags = {modeling},
researchr = {https://researchr.org/publication/BalarinY93},
cites = {0},
citedby = {0},
pages = {453-465},
booktitle = {Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL 93, sponsored by IFIP WG10.2 and in cooperation with IEE},
editor = {David Agnew and Luc J. M. Claesen and Raul Camposano},
volume = {A-32},
series = {IFIP Transactions},
publisher = {North-Holland},
isbn = {0-444-81641-0},
}