Massively parallel neural signal processing: System-on-Chip design with FPGAs

Karthikeyan Balasubramanian, Iyad Obeid. Massively parallel neural signal processing: System-on-Chip design with FPGAs. In 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2011, Boston, MA, USA, August 30 - Sept. 3, 2011. pages 4609-4612, IEEE, 2011. [doi]

@inproceedings{Balasubramanian11-0,
  title = {Massively parallel neural signal processing: System-on-Chip design with FPGAs},
  author = {Karthikeyan Balasubramanian and Iyad Obeid},
  year = {2011},
  doi = {10.1109/IEMBS.2011.6091141},
  url = {https://doi.org/10.1109/IEMBS.2011.6091141},
  researchr = {https://researchr.org/publication/Balasubramanian11-0},
  cites = {0},
  citedby = {0},
  pages = {4609-4612},
  booktitle = {33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2011, Boston, MA, USA, August 30 - Sept. 3, 2011},
  publisher = {IEEE},
  isbn = {978-1-4244-4121-1},
}