The following publications are possibly variants of this publication:
- ILP based Leakage Optimization during Nano-CMOS RTL Synthesis: A DOXCMOS Versus DTCMOS PerspectiveS. P. Mohanty, Bijaya K. Panigrahi. nabic 2009: 1367-1372 [doi]
- A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage OptimizationShibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski. jolpe, 7(4):471-481, 2011. [doi]
- An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-OptimizationShibaji Banerjee, Jimson Mathew. jolpe, 13(4):642-648, 2017. [doi]
- ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL SynthesisSaraju P. Mohanty. isqed 2008: 174-177 [doi]