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Level-2 cache for high performance /390 μ-processors

H. Barsuhn, W. Lochlein, D. Wendel, U. Wille, P. Coppens. Level-2 cache for high performance /390 μ-processors. Journal of Systems Architecture, 35(1-5):303-309, 1992. [doi]

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H. Barsuhn

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W. Lochlein

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D. Wendel

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U. Wille

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P. Coppens

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