The Speedy DDR2 Controller For FPGAs

Ray Bittner. The Speedy DDR2 Controller For FPGAs. In Toomas P. Plaks, editor, Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2009, July 13-16, 2009, Las Vegas Nevada, USA. pages 205-211, CSREA Press, 2009.

Authors

Ray Bittner

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