Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks

Cristiana Bolchini, Fabio Salice, Donatella Sciuto. Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks. In 7th Great Lakes Symposium on VLSI (GLS-VLSI 97), 13-15 March 1997, Urbana, IL, USA. pages 32, IEEE Computer Society, 1997. [doi]

@inproceedings{BolchiniSS97:1,
  title = {Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks},
  author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
  year = {1997},
  url = {http://csdl.computer.org/comp/proceedings/glsvlsi/1997/7904/00/79040032abs.htm},
  tags = {completeness, design, coverage},
  researchr = {https://researchr.org/publication/BolchiniSS97%3A1},
  cites = {0},
  citedby = {0},
  pages = {32},
  booktitle = {7th Great Lakes Symposium on VLSI (GLS-VLSI  97), 13-15 March 1997, Urbana, IL, USA},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-7904-2},
}