STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design - researchr publication authors

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Avik Bose, Prasun Ghosal, Saraju P. Mohanty. STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016. pages 496-501, IEEE, 2016. [doi]

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