A new FPGA-based DPLL algorithm to improve SAT solvers

Khadija Bousmar, Fabrice Monteiro, Zineb Habbas, Sofiène Dellagi, Abbas Dandache. A new FPGA-based DPLL algorithm to improve SAT solvers. In 27th International Conference on Microelectronics, ICM 2015, Casablanca, Morocco, December 20-23, 2015. pages 287-290, IEEE, 2015. [doi]

@inproceedings{BousmarMHDD15,
  title = {A new FPGA-based DPLL algorithm to improve SAT solvers},
  author = {Khadija Bousmar and Fabrice Monteiro and Zineb Habbas and Sofiène Dellagi and Abbas Dandache},
  year = {2015},
  doi = {10.1109/ICM.2015.7438045},
  url = {https://doi.org/10.1109/ICM.2015.7438045},
  researchr = {https://researchr.org/publication/BousmarMHDD15},
  cites = {0},
  citedby = {0},
  pages = {287-290},
  booktitle = {27th International Conference on Microelectronics, ICM 2015, Casablanca, Morocco, December 20-23, 2015},
  publisher = {IEEE},
  isbn = {978-1-4673-8759-0},
}