An FPGA/MPSoC Based Low Latency Onboard SAR Processor

Helko Breit, Srikanth Mandapati, Ulrich Balss. An FPGA/MPSoC Based Low Latency Onboard SAR Processor. In IEEE International Geoscience and Remote Sensing Symposium, IGARSS 2021, Brussels, Belgium, July 11-16, 2021. pages 5159-5162, IEEE, 2021. [doi]

@inproceedings{BreitMB21,
  title = {An FPGA/MPSoC Based Low Latency Onboard SAR Processor},
  author = {Helko Breit and Srikanth Mandapati and Ulrich Balss},
  year = {2021},
  doi = {10.1109/IGARSS47720.2021.9553539},
  url = {https://doi.org/10.1109/IGARSS47720.2021.9553539},
  researchr = {https://researchr.org/publication/BreitMB21},
  cites = {0},
  citedby = {0},
  pages = {5159-5162},
  booktitle = {IEEE International Geoscience and Remote Sensing Symposium, IGARSS 2021, Brussels, Belgium, July 11-16, 2021},
  publisher = {IEEE},
  isbn = {978-1-6654-0369-6},
}