Hao Chen, Jie Han, Fabrizio Lombardi. A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits. In 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011. pages 60-67, IEEE, 2011. [doi]
@inproceedings{ChenHL11-10,
title = {A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits},
author = {Hao Chen and Jie Han and Fabrizio Lombardi},
year = {2011},
doi = {10.1109/DFT.2011.23},
url = {http://doi.ieeecomputersociety.org/10.1109/DFT.2011.23},
researchr = {https://researchr.org/publication/ChenHL11-10},
cites = {0},
citedby = {0},
pages = {60-67},
booktitle = {2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011},
publisher = {IEEE},
isbn = {978-1-4577-1713-0},
}