A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps

Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye 0001, Junyan Ren. A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. In 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, September 23-26, 2019. pages 197-200, IEEE, 2019. [doi]

@inproceedings{ChenSNLC0R19,
  title = {A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps},
  author = {Yongzhen Chen and Xingchen Shen and Zhekan Ni and Jingchao Lan and Chixiao Chen and Fan Ye 0001 and Junyan Ren},
  year = {2019},
  doi = {10.1109/ESSCIRC.2019.8902892},
  url = {https://doi.org/10.1109/ESSCIRC.2019.8902892},
  researchr = {https://researchr.org/publication/ChenSNLC0R19},
  cites = {0},
  citedby = {0},
  pages = {197-200},
  booktitle = {45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, September 23-26, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-1550-4},
}