Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC

Yu-Jen Chen, Chen-Han Tsai, Liang-Gee Chen. Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

Authors

Yu-Jen Chen

This author has not been identified. Look up 'Yu-Jen Chen' in Google

Chen-Han Tsai

This author has not been identified. Look up 'Chen-Han Tsai' in Google

Liang-Gee Chen

This author has not been identified. Look up 'Liang-Gee Chen' in Google