Wei-Chih Chen, Shu-Chun Yang, Yu-Nan Shih, Wen-Hung Huang, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh. A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 272, IEEE, 2019. [doi]
@inproceedings{ChenYSHTH19,
title = {A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET},
author = {Wei-Chih Chen and Shu-Chun Yang and Yu-Nan Shih and Wen-Hung Huang and Chien-Chun Tsai and Kenny Cheng-Hsiang Hsieh},
year = {2019},
doi = {10.23919/VLSIC.2019.8777992},
url = {https://doi.org/10.23919/VLSIC.2019.8777992},
researchr = {https://researchr.org/publication/ChenYSHTH19},
cites = {0},
citedby = {0},
pages = {272},
booktitle = {2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019},
publisher = {IEEE},
isbn = {978-4-86348-720-8},
}