An approach to synthesis delay semantics in VHDL - researchr publication authors

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Lixin Cheng, Jinian Bian, Yunyun Liu. An approach to synthesis delay semantics in VHDL. In 11th International Conference on Computer-Aided Design and Computer Graphics, CAD/Graphics 2009, Huangshan, China, August 19-21, 2009. pages 492-496, IEEE, 2009. [doi]

This author has not been identified. Look up 'Lixin Cheng' in GoogleThis author has not been identified. Look up 'Jinian Bian' in GoogleThis author has not been identified. Look up 'Yunyun Liu' in Google

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