A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic

Kuo-Hsing Cheng, Yu-Yee Liow. A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic. In Proceedings of Third International Conference on Electronics, Circuits, and Systems, ICECS 1996, Rodos, Greece, October 13-16, 1996. pages 1037-1040, IEEE, 1996. [doi]

@inproceedings{ChengL96-1,
  title = {A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic},
  author = {Kuo-Hsing Cheng and Yu-Yee Liow},
  year = {1996},
  doi = {10.1109/ICECS.1996.584564},
  url = {https://doi.org/10.1109/ICECS.1996.584564},
  researchr = {https://researchr.org/publication/ChengL96-1},
  cites = {0},
  citedby = {0},
  pages = {1037-1040},
  booktitle = {Proceedings of Third International Conference on Electronics, Circuits, and Systems, ICECS 1996, Rodos, Greece, October 13-16, 1996},
  publisher = {IEEE},
  isbn = {0-7803-3650-X},
}