RT-level TPG Exploiting High-Level Synthesis Information

Silvia Chiusano, Fulvio Corno, Paolo Prinetto. RT-level TPG Exploiting High-Level Synthesis Information. In 17th IEEE VLSI Test Symposium (VTS 99), 25-30 April 1999, San Diego, CA, USA. pages 341-353, IEEE Computer Society, 1999. [doi]

Authors

Silvia Chiusano

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Fulvio Corno

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Paolo Prinetto

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