Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder

Chun-Yuan Chu, An-Yeu Wu. Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder. VLSI Signal Processing, 68(2):233-245, 2012. [doi]

@article{ChuW12,
  title = {Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder},
  author = {Chun-Yuan Chu and An-Yeu Wu},
  year = {2012},
  doi = {10.1007/s11265-011-0603-0},
  url = {http://dx.doi.org/10.1007/s11265-011-0603-0},
  researchr = {https://researchr.org/publication/ChuW12},
  cites = {0},
  citedby = {0},
  journal = {VLSI Signal Processing},
  volume = {68},
  number = {2},
  pages = {233-245},
}