Retargeting the MIPS-II CPU Core to the RISC-V Architecture

Sebastian Cieslak, Adrian Oleksiak, Krzysztof Marcinek, Witold A. Pleskacz. Retargeting the MIPS-II CPU Core to the RISC-V Architecture. In Andrzej Napieralksi, editor, 26th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2019, Rzeszów, Poland, June 27-29, 2019. pages 261-264, IEEE, 2019. [doi]

@inproceedings{CieslakOMP19,
  title = {Retargeting the MIPS-II CPU Core to the RISC-V Architecture},
  author = {Sebastian Cieslak and Adrian Oleksiak and Krzysztof Marcinek and Witold A. Pleskacz},
  year = {2019},
  doi = {10.23919/MIXDES.2019.8787018},
  url = {https://doi.org/10.23919/MIXDES.2019.8787018},
  researchr = {https://researchr.org/publication/CieslakOMP19},
  cites = {0},
  citedby = {0},
  pages = {261-264},
  booktitle = {26th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2019, Rzeszów, Poland, June 27-29, 2019},
  editor = {Andrzej Napieralksi},
  publisher = {IEEE},
  isbn = {978-83-63578-16-9},
}