David Crawley. A Multilevel Cache Memory Architecture for Nanoelectronics. In 9th Great Lakes Symposium on VLSI (GLS-VLSI 99), 4-6 March 1999, Ann Arbor, MI, USA. pages 346, IEEE Computer Society, 1999. [doi]
@inproceedings{Crawley99,
title = {A Multilevel Cache Memory Architecture for Nanoelectronics},
author = {David Crawley},
year = {1999},
url = {http://csdl.computer.org/comp/proceedings/glsvlsi/1999/0104/00/01040346abs.htm},
tags = {caching, architecture},
researchr = {https://researchr.org/publication/Crawley99},
cites = {0},
citedby = {0},
pages = {346},
booktitle = {9th Great Lakes Symposium on VLSI (GLS-VLSI 99), 4-6 March 1999, Ann Arbor, MI, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-0104-4},
}