Verification of asynchronous interface circuits with bounded wire delays

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang. Verification of asynchronous interface circuits with bounded wire delays. VLSI Signal Processing, 7(1-2):161-182, 1994. [doi]

Authors

Srinivas Devadas

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Kurt Keutzer

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Sharad Malik

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Albert Wang

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