Design of High-Speed Low-Power Parallel-Prefix VLSI Adders - researchr publication authors

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Giorgos Dimitrakopoulos, P. Kolovos, P. Kalogerakis, Dimitris Nikolos. Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. In Enrico Macii, Odysseas G. Koufopavlou, Vassilis Paliouras, editors, Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings. Volume 3254 of Lecture Notes in Computer Science, pages 248-257, Springer, 2004. [doi]

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