Wolfgang Ecker. Verification methods for VHDL RTL-subroutines. Journal of Systems Architecture, 42(2):117-128, 1996. [doi]
@article{Ecker96,
title = {Verification methods for VHDL RTL-subroutines},
author = {Wolfgang Ecker},
year = {1996},
doi = {10.1016/1383-7621(96)00018-5},
url = {http://dx.doi.org/10.1016/1383-7621(96)00018-5},
researchr = {https://researchr.org/publication/Ecker96},
cites = {0},
citedby = {0},
journal = {Journal of Systems Architecture},
volume = {42},
number = {2},
pages = {117-128},
}