Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT - researchr publication authors

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L. F. Fuller, C. Kraaijenvanger. Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT. In 5th Great Lakes Symposium on VLSI (GLS-VLSI 95), March 16-18, 1995, The State University of New York at Buffalo, USA. pages 238-241, IEEE Computer Society, 1995. [doi]

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