Design and Analysis of FinFET Based CSCPAL Low Power Adder

Jayashree K. G, Lois Priscilla S, Bhuvana B. P, Kanchana Bhaaskaran V. S. Design and Analysis of FinFET Based CSCPAL Low Power Adder. In IEEE International Symposium on Smart Electronic Systems, iSES 2019 (Formerly iNiS), Rourkela, India, December 16-18, 2019. pages 139-144, IEEE, 2019. [doi]

Authors

Jayashree K. G

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Lois Priscilla S

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Bhuvana B. P

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Kanchana Bhaaskaran V. S

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