Low Jitter and Low Power PLL:Towards The Utopia

Xiang Gao. Low Jitter and Low Power PLL:Towards The Utopia. In 2019 International SoC Design Conference, ISOCC 2019, Jeju, Korea (South), October 6-9, 2019. pages 38-39, IEEE, 2019. [doi]

@inproceedings{Gao19-30,
  title = {Low Jitter and Low Power PLL:Towards The Utopia},
  author = {Xiang Gao},
  year = {2019},
  doi = {10.1109/ISOCC47750.2019.9078535},
  url = {https://doi.org/10.1109/ISOCC47750.2019.9078535},
  researchr = {https://researchr.org/publication/Gao19-30},
  cites = {0},
  citedby = {0},
  pages = {38-39},
  booktitle = {2019 International SoC Design Conference, ISOCC 2019, Jeju, Korea (South), October 6-9, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-2478-0},
}