Specification and formal verification of power gating in processors

Amir Masoud Gharehbaghi, Masahiro Fujita. Specification and formal verification of power gating in processors. In Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014. pages 604-610, IEEE, 2014. [doi]

@inproceedings{GharehbaghiF14,
  title = {Specification and formal verification of power gating in processors},
  author = {Amir Masoud Gharehbaghi and Masahiro Fujita},
  year = {2014},
  doi = {10.1109/ISQED.2014.6783382},
  url = {http://dx.doi.org/10.1109/ISQED.2014.6783382},
  researchr = {https://researchr.org/publication/GharehbaghiF14},
  cites = {0},
  citedby = {0},
  pages = {604-610},
  booktitle = {Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014},
  publisher = {IEEE},
}