5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor

Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger. 5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. In 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014. pages 106-107, IEEE, 2014. [doi]

@inproceedings{GrenatPRN14,
  title = {5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor},
  author = {Aaron Grenat and Sanjay Pant and Ravinder Rachala and Samuel Naffziger},
  year = {2014},
  doi = {10.1109/ISSCC.2014.6757358},
  url = {https://doi.org/10.1109/ISSCC.2014.6757358},
  researchr = {https://researchr.org/publication/GrenatPRN14},
  cites = {0},
  citedby = {0},
  pages = {106-107},
  booktitle = {2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014},
  publisher = {IEEE},
  isbn = {978-1-4799-0918-6},
}