Chaojie He, Zi Wang, Feibin Xiang, Zhuoyu Dai, Yifan He, Jinshan Yue, Yongpan Liu. LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. IEEE Trans. Circuits Syst. II Express Briefs, 71(2):852-856, February 2024. [doi]
@article{HeWXDHYL24,
title = {LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design},
author = {Chaojie He and Zi Wang and Feibin Xiang and Zhuoyu Dai and Yifan He and Jinshan Yue and Yongpan Liu},
year = {2024},
month = {February},
doi = {10.1109/TCSII.2023.3304752},
url = {https://doi.org/10.1109/TCSII.2023.3304752},
researchr = {https://researchr.org/publication/HeWXDHYL24},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Circuits Syst. II Express Briefs},
volume = {71},
number = {2},
pages = {852-856},
}