Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang. Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. IET Circuits, Devices & Systems, 9(4):309-318, 2015. [doi]
@article{HoCGC15,
title = {Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer},
author = {Weng-Geng Ho and Kwen-Siong Chong and Bah-Hwee Gwee and Joseph S. Chang},
year = {2015},
doi = {10.1049/iet-cds.2014.0103},
url = {http://dx.doi.org/10.1049/iet-cds.2014.0103},
researchr = {https://researchr.org/publication/HoCGC15},
cites = {0},
citedby = {0},
journal = {IET Circuits, Devices & Systems},
volume = {9},
number = {4},
pages = {309-318},
}