An ultra-low power AES encryption core in 65nm SOTB CMOS process

Van-Phuc Hoang, Van-Lan Dao, Cong-Kha Pham. An ultra-low power AES encryption core in 65nm SOTB CMOS process. In International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016. pages 89-90, IEEE, 2016. [doi]

@inproceedings{HoangDP16,
  title = {An ultra-low power AES encryption core in 65nm SOTB CMOS process},
  author = {Van-Phuc Hoang and Van-Lan Dao and Cong-Kha Pham},
  year = {2016},
  doi = {10.1109/ISOCC.2016.7799747},
  url = {http://dx.doi.org/10.1109/ISOCC.2016.7799747},
  researchr = {https://researchr.org/publication/HoangDP16},
  cites = {0},
  citedby = {0},
  pages = {89-90},
  booktitle = {International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016},
  publisher = {IEEE},
  isbn = {978-1-5090-3219-8},
}