The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays - researchr publication authors

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M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas. The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. In 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA. pages 14-24, IEEE Computer Society, 2002. [doi]

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