A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks

Mingqiang Huang, Yucen Liu, Changhai Man, Kai Li, Quan Cheng, Wei Mao, Hao Yu 0001. A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap., 69(9):3619-3631, 2022. [doi]

Authors

Mingqiang Huang

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Yucen Liu

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Changhai Man

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Kai Li

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Quan Cheng

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Wei Mao

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Hao Yu 0001

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