A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth

Tsung-Chih Hung, Tai-Haur Kuo. A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth. In IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019. pages 1-4, IEEE, 2019. [doi]

@inproceedings{HungK19-1,
  title = {A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth},
  author = {Tsung-Chih Hung and Tai-Haur Kuo},
  year = {2019},
  doi = {10.1109/CICC.2019.8780368},
  url = {https://doi.org/10.1109/CICC.2019.8780368},
  researchr = {https://researchr.org/publication/HungK19-1},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019},
  publisher = {IEEE},
  isbn = {978-1-5386-9395-7},
}