Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic - researchr publication authors

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Ayse Neslin Ismailoglu, Murat Askar. Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic. In 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008. pages 1063-1066, IEEE, 2008. [doi]

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