Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits - researchr publication authors

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C. Jang, J. Kim, B. Ahn, J. Chong. Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits. IET Computers & Digital Techniques, 7(1):11-20, 2013. [doi]

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